The dual-channel architecture allows the channels to operate
either independently or in series, allowing compressed
data to be immediately decompressed to verify successful
operation. Each channel contains input and output FIFOs,
a compression/decompression engine, dedicated internal
compression memory, and command, status, and result registers.
Channel
1 performs both compression and decompression; Channel
2 performs decompression only. The two are otherwise identical.
The 9600's bus interface supports both register I/O and
DMA transfers at bus widths of 16 and 32 bits. The DMA
interface supports single-cycle bursting at a 50MHz bus
speed. Though fast, the bus interface is straightforward
and easy to interface to. Verilog models are also available.
Features
- Dual-channel
compressor/decompressor
-
75MB/s per channel in either compression or decompression
- Industry-standard
LZS algorithm.
- Supports
simultaneous full-speed compression and decompression
- On-the-fly
output stream verification ("feedback mode") during
compression processes multiple data records per command
- On-chip
memory eliminates the need for external compression
RAM
- High-speed,
single-cycle burst interface
- Straightforward
I/O interface for easy integration
