Industry Standard LZS Compression at a Racing 300 Megabytes Per Second

Introducing the high performance Hifn 9630 lossless data compression processor. The 9630, using Hifn’s industry-standard LZS algorithm, can compress or decompress data at up to 300 Mbytes/s, fast enough to support SCSI-3 devices and beyond. The 9630 verifies every compressed packet, delivering 100% accuracy on your data.

The 9630 verifies the results of the compression engine in real time. In compression mode, the compression engine compresses the input data, while the decompression engine decompresses the output of the compression engine and verifies the resulting CRC.

The 9630 has a pair of 64-byte FIFOs that buffer data to and from the system bus. A 4K-byte SRAM is used to store the compressed data while the output is being verified. These FIFOs allow both engines to operate at full speed over the system bus. The 9630 uses DMA handshaking signals to control the movement of data into and out of the Source and Destination FIFOs.

The 9630 system bus interface supports both register I/O and single-cycle burst DMA transfers. The system interface is 16-bits wide, separate input and output data buses, and operates at 150 MHz.

Hifn’s LZS compression algorithm has been standardized by many organizations, including ANSI (X.3.241), QIC (122), IETF (RFC 1967, RFC 1974), TIA/EIA (655), and the Frame Relay Forum (FRF.9).

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