Network-on-a-chip ('''NoC''') is a new approach to System-on-a-chip ('''SoC''') design. NoC-based systems accommodate multiple asynchronous Clocking that many of today's complex SoC designs use. The '''NoC''' solution brings a networking method to on-chip Communication and claims roughly a threefold performance increase over conventional bus systems. == Emerging Paradigm == Network-on-Chip ('''NoC''') is an emerging Paradigm for Communications within large VLSI systems implemented on a single silicon chip. In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange Data encoded in packets of bits, using a network as a "public transportation" sub-system for the information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source Module to any destination Module over several links, by making routing decisions at the switches. An '''NoC''' is similar to a modern Telecommunications_network, using digital bit-packet switching over multiplexed links. == Parallelism and Scalability == The wires in the links of the '''NoC''' are shared by many signals. A high level of Parallelism is achieved, because all links in the '''NoC''' can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, an '''NoC''' provides enhanced performance and Scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). == Benefits of Adopting NoCs == The adoption of NoC architecture is driven by several forces: from a physical design viewpoint, in Nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. '''NoC''' links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. An '''NoC''' can provide separation between Computation and Communication, support modularity and IP reuse via standard interfaces, handle Synchronization issues, serve as a platform for System_test, and, hence, increase engineering productivity. == Research on On-chip Networks == Although '''NoC'''s can borrow concepts and techniques from the well-established domain of Computer_networking, it is impractical to blindly reuse features of "classical" computer networks and symmetric multiprocessors. In particular, '''NoC''' switches must be small, energy-efficient, and fast. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Network_topology and properties may be application-specific. '''NoC'''s need to support Quality_of_service, namely achieve the various requirements in terms of Throughput, end-to-end delays and deadlines. To date, several Prototype '''NoC'''s have been designed, analyzed and implemented in both industry and academia (see materials of the 2006 full-day workshop on NoCs). However, many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on Networks on Chip will be held in Princeton, NJ, in May 2007. == References ==
  1. Jantsch, J. Oberg and H. Tenhunen (Eds.), Journal of System Architecture, special issue on networks on chip, Volume 50, Issues 2-3, Pages 61-168 (February 2004).
  2. L. Benini (Ed.), Integration . the VLSI journal, special issue on networks on chip, Volume 38, Issue 1, Pages 1-130 (October 2004).
  3. A. Jantsch and H. Tenhunen (Eds.), "Networks on Chip," Kluwer Academic Publishers, 2003.
  4. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "QNoC: QoS architecture and design process for cost-effective Network on Chip," The Journal of Systems Architecture, Volume 50, pp. 105-128, February 2004.
  5. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny , "Cost considerations in Network on Chip," Integration - the VLSI journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004.
  6. NoC 2006
  7. On-Chip Networks Bibliography
== See also == *Electronic_design_automation *Integrated_circuit_design ---- Category:Integrated_circuits Category:Electronic_design_automation ---- Adapted from Avinoam Kolodny's's column in the ACM SIGDA e-newsletter by Igor Markov
The original text can be found at http://www.sigda.org/newsletter/2006/060415.txt