Pentium

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Pentium
Central processing unit

75 MHz classic Pentium processor
Produced	From 1993 to 1999
Common manufacturer(s)	Intel
Max CPU clock	60 MHz to 300 MHz
FSB speeds	50  to 66
Min feature size	0.8 µm to 0.25 µm
Instruction set	x86
Microarchitecture	P5
Cores	1
Socket(s)	Socket 4, Socket 5, Socket 7
Core name(s)	P5. P54, P54CS, P55C, Tillamook

The Pentium^[1] brand refers to Intel's single-core x86 microprocessor^[2] based on the P5 fifth-generation microarchitecture. The name Pentium was derived from the Greek pente (πέντε), meaning 'five', and the Latin ending -ium.

Introduced on March 22, 1993^[3], the Pentium succeeded the Intel486, in which the number "4" signified the fourth-generation microarchitecture. Intel selected the Pentium name after courts had disallowed trademarking of names containing numbers - like "286", "i386", "i486" - though, sometimes, the Pentium is unofficially referred to as i586. In 1996, the original Pentium was succeeded by the Pentium MMX branded CPUs still based on the P5 fifth-generation microarchitecture.

Starting in 1995, Intel used the "Pentium" registered trademark in the names of families of post-fifth-generations of x86 processors branded as the Pentium Pro, Pentium II, Pentium III, Pentium 4 and Pentium D (see Pentium (brand)). Although they shared the x86 instruction set with the original Pentium (and its predecessors), their microarchitectures were radically different from the P5 microarchitecture of CPUs branded as Pentium or Pentium MMX. In 2006, the Pentium briefly disappeared from Intel's roadmaps^[4][5] to reemerge in 2007 and solidify in 2008^[6].

Vinod Dham is often referred to as the father of the Intel Pentium processor,^[7][8] although many people, including John H. Crawford (of i386 and i486 alumni), was involved in the design and development of the processor.

[edit] Improvements over i486

Pentium Overdrive for i486 systems

• Superscalar architecture - The Pentium has two datapaths (pipelines) that allow it to complete more than one instruction per clock cycle. One pipe (called U) can handle any instruction, while the other (called V) can handle the simplest, most common instructions. Some RISC-proponents argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined microarchitecture, much less by a dual pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible.
• 64-bit external databus width - This doubles the amount of information read or written on each memory access. This doesn't mean that the Pentium can execute 64-bit applications; its main registers are still 32 bits wide.
• Faster floating point unit.
• MMX instructions (later models only) - A basic SIMD instruction set extension designed for use in multimedia applications.

Pentium architecture chips offered just under twice the performance of a 486 processor per clock cycle. The fastest Intel 486 parts were almost as powerful as a first-generation Pentium, and the AMD Am5x86 was roughly equal to the Pentium 75.

The Pentium ("Classic") series were designed to run at over 100 million instructions per second (MIPS), [1] with the 75 MHz model running at 126.5 MIPS. [2]

[edit] Models

The earliest Pentiums were released at the clock speeds of 66 MHz and 60 MHz. Later on 75, 90, 100, 120, 133, 150, 166, 200, and 233 MHz versions gradually became available. 266 and 300 MHz versions were later released for mobile computing. Pentium OverDrive processors were released at speeds of 63 and 83 MHz as an upgrade option for older 486-class computers.

Pentium 66 MHz and 60 MHz chips contained 3.1 million transistors.

• * These were only available as Mobile Pentium MMX chips for laptops.

[edit] P5, P54C, P54CS

Pentium logo, with MMX enhancement

The original Pentium microprocessor had the internal code name P5 and the product code 80501 (80500 for the earliest steppings). This was a pipelined in-order superscalar microprocessor, produced using a 0.8 µm process. It was followed by the P54C (80502), built on a 0.6 µm process and employing an internal clock multiplier to let the internal circuitry work at a higher frequency than the external bus (as it is much more cumbersome to increase the bus frequency). It was also dual-processor ready. The P54C was followed by the P54CS, built on a 0.35 µm process.

[edit] Bugs and problems

The early versions of 60-100 MHz Pentiums had a problem in the floating point unit that, in rare cases, resulted in reduced precision of division operations. This bug, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became known as the Pentium FDIV bug and caused embarrassment for Intel, which created an exchange program to replace the faulty processors. Soon afterwards, a bug was discovered which could allow a malicious program to crash a system without any special privileges (the f00f bug); fortunately, operating systems were able to implement workarounds to prevent crashes.

The 60 and 66 MHz 0.8 µm versions of the Pentium processors also had (for the time) high heat production due to their 5V operation. The P54C used 3.3V and had significantly lower power draw (a quadratic relationship). P5 Pentiums used Socket 4, while P54C started out on Socket 5 before moving to Socket 7 in later revisions. All desktop Pentiums from P54CS onwards used Socket 7.

[edit] Pentium Overdrive

The P24T Pentium OverDrive for 486-systems were released in 1995, which were based on 3.3V 0.6 µm versions using a 63 or 83 MHz clock. Since these used Socket 2/3, some adjustment had to be made to compensate for the 32-bit data bus and slower on-board L2 cache of 486-motherboards. They were therefore equipped with a 32KB L1 cache (double that of pre-P55C Pentiums). The product included an attached fan and heatsink assembly as well as power regulation to convert 5V down to 3.3V. Intel had promised 486 users an upgrade in the "near future" via an "Overdrive" socket to accommodate a Pentium-like CPU. However, the P24T arrived late, at low speeds, and high costs, which led some users to suspect that Intel never really planned such an upgrade, but eventually offered it to avoid a lawsuit. The P24Ts therefore sold poorly. In addition, motherboard compatibility with the P24T was poor, possibly due to the use of a write-back caching scheme. Common workarounds were to disable the motherboard's L2 cache causing a noticeable drop in system performance.

[edit] P55C, Tillamook

Pentium MMX 233 MHz (P55C, 80503) top

Pentium MMX 166 MHz without cover

Pentium III chip mounted on a motherboard

The P55C (or 80503) was developed by Intel's Research & Development Center in Haifa, Israel. It was sold as Pentium with MMX Technology (usually just called Pentium MMX); although it was based on the P5 core (the 0.35 µm process was also used for this series) it featured a new set of 57 "MMX" instructions intended to improve performance on multimedia tasks, such as encoding and decoding digital media data.

The new instructions work on new data types: 64-bit packed vectors of either eight 8-bit integers, four 16-bit integers, two 32-bit integers, or one 64-bit integer. So, for example, the PADDUSB (Packed ADD Unsigned Saturated Byte) instruction adds two vectors, each containing eight 8-bit unsigned integers together, pairwise; each addition that would overflow saturates, yielding 255, the maximum unsigned value that can be represented in a byte. These rather specialized instructions generally require special coding by the programmer for them to be used. MMX did not achieve significant popularity until after the P55C's lifetime^{[citation needed]}.

The performance of the P55C was improved over previous versions by a doubling of the Level 1 CPU cache from 16 KiB to 32 KiB.

Pentium P55C notebook CPUs used a "mobile module" that held the CPU. This module was a PCB with the CPU directly attached to it in a special smaller form factor. The module snapped to the notebook motherboard and typically a heat spreader plate was installed and made contact with the module. Such notebooks frequently used the Intel 430MX chipset, a feature-reduced 430FX. However, with the 0.25 µm Tillamook Mobile Pentium MMX (named after a city in Oregon), the module also held the 430TX chipset along with the system's 512 KiB SRAM cache memory.

[edit] As a trademark

Main article: Pentium (brand)

Intel used the "Pentium" trademark in many brand names of x86 (instruction set) processors of later generations with different microarchitectures radically departed from the P5 found in CPUs originally branded as the "Pentium" only. They include:

• Pentium Pro
• Pentium II, Pentium II Xeon
• Pentium III, Pentium III Xeon
• Pentium 4, Mobile Pentium 4, Mobile Pentium 4 M, Pentium 4 Extreme Edition
• Pentium M
• Pentium D, Pentium Extreme Edition
• Pentium Dual-Core

[edit] Competitors

• AMD K5, AMD K6
• Cyrix 6x86
• WinChip C6
• NexGen Nx586
• Rise mP6

[edit] See also

• Vinod Dham
• CPU design
• COASt (Cache On A Stick), L2 cache modules for Pentium
• IA-32 instruction set architecture (ISA)
• Pentium Compatible Processor

[edit] References

[edit] External links

• CPU-Collection.de - Intel Pentium images and descriptions
• Plasma Online Intel CPU Identification
• Pictures of all known Pentium chips at chipdb.org
• Pentium ES timeline Timeline with Pentium engineering samples and oldest known non-ES in correlation to their official release date.